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19-1003; Rev 1; 11/04
KIT ATION EVALU ABLE AVAIL
1.8V, 12-Bit, 170Msps ADC for Broadband Applications
General Description Features
170Msps Conversion Rate Low Noise Floor of -68dBFS Excellent Low-Noise Characteristics SNR = 65.2dB at fIN = 65MHz SNR = 62.8dB at fIN = 250MHz Excellent Dynamic Range SFDR = 78dBc at fIN = 65MHz SFDR = 71.4dBc at fIN = 250MHz 62.2dB NPR for fNOTCH = 22MHz and a Noise Bandwidth of 35MHz Single 1.8V Supply 975mW Power Dissipation at fSAMPLE = 170Msps and fIN = 65MHz On-Chip Track-and-Hold Amplifier Internal 1.24V-Bandgap Reference On-Chip Selectable Divide-by-2 Clock Input LVDS Digital Outputs with Data Clock Output MAX1213 EV Kit Available
MAX1213
The MAX1213 is a monolithic, 12-bit, 170Msps analogto-digital converter (ADC) optimized for outstanding dynamic performance at high-IF frequencies up to 300MHz. The product operates with conversion rates up to 170Msps while consuming only 975mW. At 170Msps and an input frequency up to 250MHz, the MAX1213 achieves a spurious-free dynamic range (SFDR) of 71.4dBc. Its excellent signal-to-noise ratio (SNR) of 65.5dB at 10MHz remains flat (within 3dB) for input tones up to 250MHz. This ADC yields an excellent low-noise floor of -68dBFS, which makes it ideal for wideband applications such as cable head-end receivers and power-amplifier predistortion in cellular base-station transceivers. The MAX1213 requires a single 1.8V supply. The analog input is designed for either differential or single-ended operation and can be AC- or DC-coupled. The ADC also features a selectable on-chip divide-by-2 clock circuit, which allows the user to apply clock frequencies as high as 340MHz. This helps to reduce the phase noise of the input clock source. A low-voltage differential signal (LVDS) sampling clock is recommended for best performance. The converter's digital outputs are LVDS compatible and the data format can be selected to be either two's complement or offset binary. The MAX1213 is available in a 68-pin QFN package with exposed paddle (EP) and is specified over the industrial (-40C to +85C) temperature range. Pin-compatible 8-bit and 10-bit versions of the MAX1213 are also available. Refer to the MAX1121 (8 bits, 250Msps), MAX1122 (10 bits, 170Msps), MAX1123 (10 bits, 210Msps), and the MAX1124 (10 bits, 250Msps) data sheets for more information. See Table 2.
Pin Configuration
TOP VIEW
OGND AGND AGND AGND D11N D10N OVCC D11P D10P AVCC AVCC AVCC ORN ORP D9N
51
68
67 66 65 64
63 62 61 60 59 58
57 56 55 54 53 52
AVCC AGND REFIO REFADJ AGND AVCC AGND INP INN AVCC
D9P
T/B
1 2 3 4 5 6 7 8 9
D8P D8N D7P D7N D6P D6N OGND OVCC DCLKP DCLKN OVCC D5P D5N D4P D4N D3P D3N
EP
50 49 48 47 46 45 44
Applications
Base-Station Power-Amplifier Linearization Cable Head-End Receivers Wireless and Wired Broadband Communication Communications Test Equipment Radar and Satellite Subsystems
MAX1213
43 42 41 40 39 38 37 36 35
AGND 10
11
AVCC 12 AVCC 13 AVCC 14 AGND 15 AGND 16 CLKDIV 17
Ordering Information
PART MAX1213EGK TEMP RANGE -40C to +85C PIN-PACKAGE 68 QFN-EP*
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
AGND
AVCC
CLKN
D1N
D2N
D0P
D1P
AVCC
OVCC
OVCC
CLKP
*EP = Exposed paddle.
QFN
________________________________________________________________ Maxim Integrated Products
OGND
AGND
AGND
AGND
D0N
D2P
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
1.8V, 12-Bit, 170Msps ADC for Broadband Applications MAX1213
ABSOLUTE MAXIMUM RATINGS
AVCC to AGND ..................................................... -0.3V to +2.1V OVCC to OGND .................................................... -0.3V to +2.1V AVCC to OVCC ...................................................... -0.3V to +2.1V AGND to OGND ................................................... -0.3V to +0.3V INP, INN to AGND ....................................-0.3V to (AVCC + 0.3V) All Digital Inputs to AGND........................-0.3V to (AVCC + 0.3V) REFIO, REFADJ to AGND ........................-0.3V to (AVCC + 0.3V) All Digital Outputs to OGND ....................-0.3V to (OVCC + 0.3V) ESD on All Pins (Human Body Model) .............................2000V Continuous Power Dissipation (TA = +70C) 68-Pin QFN (derate 41.7mW/C above +70C) .........3333mW Operating Temperature Range ...........................-40C to +85C Junction Temperature .....................................................+150C Storage Temperature Range ............................-60C to +150C Maximum Current into Any Pin............................................50mA Lead Temperature (soldering,10s) ..................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AVCC = OVCC = 1.8V, AGND = OGND = 0, fSAMPLE = 170MHz, differential sine-wave clock input drive, 0.1F capacitor on REFIO, internal reference, digital output pins differential RL = 100 1%, TA = TMIN to TMAX, unless otherwise noted. +25C guaranteed by production test, <+25C guaranteed by design and characterization. Typical values are at TA = +25C.)
PARAMETER DC ACCURACY Resolution Integral Nonlinearity (Note 1) Differential Nonlinearity (Note 1) Transfer Curve Offset Offset Temperature Drift ANALOG INPUTS (INP, INN) Full-Scale Input Voltage Range Full-Scale Range Temperature Drift Common-Mode Input Range Input Capacitance Differential Input Resistance Full-Power Analog Bandwidth REFERENCE (REFIO, REFADJ) Reference Output Voltage Reference Temperature Drift REFADJ Input High Voltage SAMPLING CHARACTERISTICS Maximum Sampling Rate Minimum Sampling Rate Clock Duty Cycle Aperture Delay Aperture Jitter tAD tAJ fSAMPLE fSAMPLE Set by clock-management circuit Figures 4, 11 Figure 11 170 20 40-60 620 0.2 Msps Msps % ps psRMS VREFADJ Used to disable the internal reference AVCC - 0.3 VREFIO TA = +25C, REFADJ = AGND 1.18 1.24 90 1.30 V ppm/C V VCM CIN RIN FPBW 3.00 VFS TA = +25C (Note 1) 1375 1485 130 1.365 0.15 3 4.3 900 6.25 1585 mVP-P ppm/C V pF k MHz INL DNL VOS fIN = 10MHz, TA = +25C fIN = 10MHz (Note 2) TA = +25C No missing codes (Note 2) TA = +25C (Note 1) 12 -1.5 -2.35 -1 -1 -2.5 40 0.5 0.5 0.25 0.25 +1.5 +2.35 +1 +1.5 +2.5 Bits LSB LSB mV mV/C SYMBOL CONDITIONS MIN TYP MAX UNITS
2
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1.8V, 12-Bit, 170Msps ADC for Broadband Applications
ELECTRICAL CHARACTERISTICS (continued)
(AVCC = OVCC = 1.8V, AGND = OGND = 0, fSAMPLE = 170MHz, differential sine-wave clock input drive, 0.1F capacitor on REFIO, internal reference, digital output pins differential RL = 100 1%, TA = TMIN to TMAX, unless otherwise noted. +25C guaranteed by production test, <+25C guaranteed by design and characterization. Typical values are at TA = +25C.)
PARAMETER CLOCK INPUTS (CLKP, CLKN) Differential Clock Input Amplitude Clock Input Common-Mode Voltage Range Clock Differential Input Resistance Clock Differential Input Capacitance RCLK CCLK (Note 2) 200 500 1.15 0.25 11 25% 5 mVP-P V k pF SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX1213
DYNAMIC CHARACTERISTICS (at -2dBFS) fIN = 10MHz, TA = +25C Signal-to-Noise Ratio SNR fIN = 65MHz, TA = +25C fIN = 190MHz fIN = 250MHz fIN = 10MHz, TA = +25C Signal-to-Noise and Distortion SINAD fIN = 65MHz, TA = +25C fIN = 190MHz fIN = 250MHz fIN = 10MHz, TA = +25C Spurious-Free Dynamic Range SFDR fIN = 65MHz, TA = +25C fIN = 190MHz fIN = 250MHz fIN = 10MHz, TA = +25C Worst Harmonics (HD2 or HD3) fIN = 65MHz, TA = +25C fIN = 190MHz fIN = 250MHz Two-Tone Intermodulation Distortion Noise Power Ratio TTIMD NPR fIN1 = 209MHz at -7dBFS, fIN2 = 210MHz at -7dBFS fNOTCH = 22MHz 1MHz, noise BW = 35MHz, AIN = -9.1dBFS RL = 100 1% RL = 100 1% 250 1.125 77 73 64 63.5 64 64 65.5 65.2 64 62.8 65.4 64.9 62.9 62.3 85 78 69.7 71.4 -85 -78 -69.7 -71.4 -66.7 62.2 dBc dB -77 -73 dBc dBc dB dB
LVDS DIGITAL OUTPUTS (D0P/N-D11P/N, ORP/N) Differential Output Voltage Output Offset Voltage |VOD| OVOS 400 1.310 mV V
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3
1.8V, 12-Bit, 170Msps ADC for Broadband Applications MAX1213
ELECTRICAL CHARACTERISTICS (continued)
(AVCC = OVCC = 1.8V, AGND = OGND = 0, fSAMPLE = 170MHz, differential sine-wave clock input drive, 0.1F capacitor on REFIO, internal reference, digital output pins differential RL = 100 1%, TA = TMIN to TMAX, unless otherwise noted. +25C guaranteed by production test, <+25C guaranteed by design and characterization. Typical values are at TA = +25C.)
PARAMETER Digital Input Voltage Low Digital Input Voltage High TIMING CHARACTERISTICS CLK-to-Data Propagation Delay CLK-to-DCLK Propagation Delay DCLK-to-Data Propagation Delay LVDS Output Rise Time LVDS Output Fall Time Output Data Pipeline Delay POWER REQUIREMENTS Analog Supply Voltage Range Digital Supply Voltage Range Analog Supply Current Digital Supply Current Analog Power Dissipation Power-Supply Rejection Ratio (Note 3) AVCC OVCC IAVCC IOVCC PDISS PSRR fIN = 65MHz fIN = 65MHz fIN = 65MHz Offset Gain 1.70 1.70 1.80 1.80 483 58 975 1.8 1.5 1.90 1.90 555 67 1120 V V mA mA mW mV/V %FS/V tPDL tCPDL tRISE tFALL tLATENCY Figure 4 Figure 4 2.5 20% to 80%, CL = 5pF 20% to 80%, CL = 5pF Figure 4 1.85 4.815 2.965 460 460 11 3.4 ns ns ns ps ps Clock cycles SYMBOL VIL VIH 0.8 x AVCC CONDITIONS MIN TYP MAX 0.2 x AVCC UNITS V V LVCMOS DIGITAL INPUTS (CLKDIV, T/B)
tPDL - tCPDL Figure 4 (Note 2)
Note 1: Static linearity and offset parameters are based on the end-point fit method. The full-scale range (FSR) is defined as 4095 x slope of the line. Note 2: Parameter guaranteed by design and characterization: TA = TMIN to TMAX. Note 3: PSRR is measured with both analog and digital supplies connected to the same potential.
4
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1.8V, 12-Bit, 170Msps ADC for Broadband Applications
Typical Operating Characteristics
(AVCC = OVCC = 1.8V, AGND = OGND = 0, fSAMPLE = 170MHz, AIN = -1dBFS; see each TOC for detailed information on test conditions, differential input drive, differential sine-wave clock input drive, 0.1F capacitor on REFIO, internal reference, digital output pins differential RL = 100, TA = +25C.)
FFT PLOT (16,384-POINT DATA RECORD)
MAX1213 toc01
MAX1213
FFT PLOT (16,384-POINT DATA RECORD)
MAX1213 toc02
FFT PLOT (16,384-POINT DATA RECORD)
-10 -20 -30 AMPLITUDE (dB) -40 -50 -60 -70 -80 -90 -100 -110 7 fIN = 190.0004293MHz fSAMPLE = 170.005299MHz AIN = -1.092dBFS SNR = 65dB SINAD = 64.1dB SFDR = 73.3dBc HD2 = -78.2dBc HD3 = -73.3dBc 3 2 5 6 4
MAX1213 toc03
0 -10 -20 -30 AMPLITUDE (dB) -40 -50 -60 -70 -80 -90 -100 -110 0 10 2
AMPLITUDE (dB)
fIN = 13.0015039MHz fSAMPLE = 170.005299MHz AIN = -1.073dBFS SNR = 66.6dB SINAD = 66.5dB SFDR = 84.5dBc HD2 = -89.5dBc HD3 = -84.5dBc 3 4 5 6
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110
fIN = 65.1112825MHz fSAMPLE = 170.005299MHz AIN = -1.099dBFS SNR = 66.3dB SINAD = 66.2dB SFDR = 74.8dBc HD2 = -82.4dBc HD3 = -75.6dBc 3 2 6 5 4 7
0
7
40 50 60 70 80 ANALOG INPUT FREQUENCY (MHz)
20
30
0
10
40 50 60 70 80 ANALOG INPUT FREQUENCY (MHz)
20
30
0
10
20 30 40 50 60 70 80 ANALOG INPUT FREQUENCY (MHz)
FFT PLOT (16,384-POINT DATA RECORD)
MAX1213 toc04
TWO-TONE IMD PLOT (16,384-POINT DATA RECORD)
MAX1213 toc05
TWO-TONE IMD PLOT (16,384-POINT DATA RECORD)
-10 -20 -30 AMPLITUDE (dB) -40 -50 -60 -70 -80 -90 -100 -110 2fIN1 - fIN2 fIN2 fIN1 = 200.0031825MHz fIN2 = 201.0200599MHz fSAMPLE = 170.005299MHz AIN1 = AIN2 = -7dBFS IMD = -65.5dBc fIN1 2fIN1 - fIN2
MAX1213 toc06 MAX1213 toc09
0 -10 -20 -30 AMPLITUDE (dB) -40 -50 -60 -70 -80 -90 -100 -110 0
AMPLITUDE (dB)
fIN = 249.9131855MHz fSAMPLE = 170.005299MHz AIN = -1.051dBFS SNR = 64.4dB SINAD = 63.3dB SFDR = 71dBc HD2 = -90.4dBc HD3 = -71dBc 5 2 6 4 7
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 2fIN1 - fIN2 2fIN2 - fIN1 fIN1 fIN1 = 29.5205735MHz fIN2 = 30.5166983MHz fSAMPLE = 170.005299MHz AIN1 = AIN2 = -7dBFS IMD = -81.8dBc fIN2
0
3
10
40 50 60 70 80 ANALOG INPUT FREQUENCY (MHz)
20
30
0
10
40 50 60 70 80 ANALOG INPUT FREQUENCY (MHz)
20
30
0
10
20 30 40 50 60 70 80 ANALOG INPUT FREQUENCY (MHz)
SNR/SINAD vs. ANALOG INPUT FREQUENCY (fSAMPLE = 170.0053MHz, AIN = -1dBFS)
MAX1213 toc07
SFDR vs. ANALOG INPUT FREQUENCY (fSAMPLE = 170.0053MHz, AIN = -1dBFS)
85 80 75 SFDR (dBc)
MAX1213 toc08
HD2/HD3 vs. ANALOG INPUT FREQUENCY (fSAMPLE = 170.0053MHz, AIN = -1dBFS)
-60 -65 HD3 -70 HD2/HD3 (dBc) -75 -80 -85 -90 -95 -100 0 50 100 150 200 250 HD2
70 SNR
90
67 SNR/SINAD (dB)
64 SINAD 61
70 65 60 55
58
50 45
55 0 50 100 150 200 250 ANALOG INPUT FREQUENCY (MHz)
40 0 50 100 150 200 250 ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
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5
1.8V, 12-Bit, 170Msps ADC for Broadband Applications MAX1213
Typical Operating Characteristics (continued)
(AVCC = OVCC = 1.8V, AGND = OGND = 0, fSAMPLE = 170MHz, AIN = -1dBFS; see each TOC for detailed information on test conditions, differential input drive, differential sine-wave clock input drive, 0.1F capacitor on REFIO, internal reference, digital output pins differential RL = 100, TA = +25C.)
SNR/SINAD vs. ANALOG INPUT AMPLITUDE (fSAMPLE = 170.0053MHz, fIN = 65.1113MHz)
MAX1213 toc10
SFDR vs. ANALOG INPUT AMPLITUDE (fSAMPLE = 170.0053MHz, fIN = 65.1113MHz)
MAX1213 toc11
HD2/HD3 vs. ANALOG INPUT AMPLITUDE (fSAMPLE = 170.0053MHz, fIN = 65.1113MHz)
MAX1213 toc12
68 62 SNR/SINAD (dB) 56 SNR
80 75 70 SFDR (dBc)
-50
-60 HD2/HD3 (dBc)
HD3
SINAD 50 44 38 32 -30 -25 -20 -15 -10 -5 0 ANALOG INPUT AMPLITUDE (dBFS)
-70
65 60 55 50 -30 -25 -20 -15 -10 -5 0 ANALOG INPUT AMPLITUDE (dBFS)
-80 HD2
-90
-100 -30 -25 -20 -15 -10 -5 0 ANALOG INPUT AMPLITUDE (dBFS)
SNR/SINAD vs. fSAMPLE (fIN = 65MHz, AIN = -1dBFS)
MAX1213 toc13
SFDR vs. fSAMPLE (fIN = 65MHz, AIN = -1dBFS)
MAX1213 toc14
HD2/HD3 vs. fSAMPLE (fIN = 65MHz, AIN = -1dBFS)
-65 -70 -75 HD2/HD3 (dBc) -80 -85 -90 -95 -100 -105 -110 HD2 HD3
MAX1213 toc15
68 67 66 SNR/SINAD (dB) SNR
90 85 80 SFDR (dBc) 75 70 65 60 55 50
-60
65 64 63 62 61 60 20 50 80 110 140 170 200 fSAMPLE (MHz) SINAD
20
50
80
110
140
170
200
20
40
60
80 100 120 140 160 180 200 fSAMPLE (MHz)
fSAMPLE (MHz)
6
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1.8V, 12-Bit, 170Msps ADC for Broadband Applications
Typical Operating Characteristics (continued)
(AVCC = OVCC = 1.8V, AGND = OGND = 0, fSAMPLE = 170MHz, AIN = -1dBFS; see each TOC for detailed information on test conditions, differential input drive, differential sine-wave clock input drive, 0.1F capacitor on REFIO, internal reference, digital output pins differential RL = 100, TA = +25C.)
TOTAL POWER DISSIPATION vs. fSAMPLE (fIN = 65MHz, AIN = -1dBFS)
MAX1213 toc16
MAX1213
INL vs. DIGITAL OUTPUT CODE (1,048,576-POINT DATA RECORD)
MAX1213 toc17
DNL vs. DIGITAL OUTPUT CODE (1,048,576-POINT DATA RECORD)
0.8 0.6 0.4 DNL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 fIN = 13.0015039MHz
MAX1213 toc18
1000 990 980 970 PDISS (mW)
1.5 1.0 0.5 INL (LSB) 0 -0.5 -1.0 -1.5
fIN = 13.0015039MHz
1.0
960 950 940 930 920 910 900 20 40 60 80 100 120 140 160 180 200 fSAMPLE (MHz)
-1.0 0 512 1024 1536 2048 2560 3072 3584 4096 DIGITAL OUTPUT CODE 0 512 1024 1536 2048 2560 3072 3584 4096 DIGITAL OUTPUT CODE
GAIN BANDWIDTH PLOT (fSAMPLE = 170.0053MHz, AIN = -1dBFS)
0 -1 GAIN (dB) -2 -3 -4 -5 -6 -7 10 100 ANALOG INPUT FREQUENCY (MHz) 1000 62 61 -40 SNR/SINAD (dB) 65 64
MAX1213 toc19
SNR/SINAD vs. TEMPERATURE (fSAMPLE = 170MHz, AIN = -2dBFS)
MAX1213 toc20
1
67 66 SNR
SINAD 63
fIN = 65MHz -15 10 35 60 85
TEMPERATURE (C)
SFDR vs. TEMPERATURE (fSAMPLE = 170MHz, AIN = -2dBFS)
MAX1213 toc21a
HD2/HD3 vs. TEMPERATURE (fSAMPLE = 170MHz, AIN = -2dBFS)
-65 -70 HD2/HD3 (dBc) -75 -80 -85 -90 -95 HD2 fIN = 65MHz -40 -15 10 35 60 85 HD3
MAX1213 toc21b
82 81 80 79 SFDR (dBc) 78 77 76 75 74 73 72 -40 -15 10 35 TEMPERATURE (C) fIN = 65MHz 60
-60
-100 85 TEMPERATURE (C)
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7
1.8V, 12-Bit, 170Msps ADC for Broadband Applications MAX1213
Typical Operating Characteristics (continued)
(AVCC = OVCC = 1.8V, AGND = OGND = 0, fSAMPLE = 170MHz, AIN = -1dBFS; see each TOC for detailed information on test conditions, differential input drive, differential sine-wave clock input drive, 0.1F capacitor on REFIO, internal reference, digital output pins differential RL = 100, TA = +25C.)
SNR/SINAD vs. SUPPLY VOLTAGE (fIN = 65.1113MHz, AIN = -1dBFS)
MAX1213 toc22
INTERNAL REFERENCE vs. SUPPLY VOLTAGE
MAX1213 toc23
tPDL/tCPDL vs. TEMPERATURE
MAX1213 toc24
68 67 66 SNR/SINAD (dB) AVCC = OVCC
1.2440
MEASURED AT REFIO REFADJ = AVCC = AGND
6 5 4
1.2430
64 63 62 61 60 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 SUPPLY VOLTAGE (V)
VREFIO (V)
1.2420
tPDL/tCPDL (ns)
65
tCPDL tPDL
3 2 1 0
1.2410
1.2400
1.2390 1.6 1.7 1.8 1.9 2.0 2.1 SUPPLY VOLTAGE (V)
-40
-15
10
35
60
85
TEMPERATURE (C)
NPR vs. ANALOG INPUT POWER
MAX1213 toc25
NOISE-POWER RATIO PLOT (WIDE NOISE BANDWIDTH: 50MHz)
MAX1213 toc26
NOISE-POWER RATIO PLOT (NARROW NOISE BANDWIDTH: 35MHz)
-20 -30 NPR (dB) -40 -50 -60 -70
MAX1213 toc27
65 fNOTCH = 22MHz 1MHz 61
-10 -20 -30
-10
NPR (dB)
NPR (dB)
57
-40 -50 -60 -70 -80 fNOTCH = 22MHz
53
49
-80 fNOTCH = 22MHz -90 0 5 10 15 20 25 30 35
45 -16 -15 -14 -13 -12 -11 -10 -9 -8 -7 ANALOG INPUT POWER (dBFS)
-90 0 5 10 15 20 25 30 35 40 45 50 ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
8
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1.8V, 12-Bit, 170Msps ADC for Broadband Applications
Pin Description
PIN 1, 6, 11-14, 20, 25, 62, 63, 65 2, 5, 7, 10, 15, 16, 18, 19, 21, 24, 64, 66, 67 NAME AVCC FUNCTION Analog Supply Voltage. Bypass each pin with a parallel combination of 0.1F and 0.22F capacitors for best decoupling results. Analog Converter Ground
MAX1213
AGND
3
REFIO
Reference Input/Output. With REFADJ pulled high, this I/O port allows an external reference source to be connected to the MAX1213. With REFADJ pulled low, the internal 1.24V bandgap reference is active. Reference Adjust Input. REFADJ allows for FSR adjustments by placing a resistor or trim potentiometer between REFADJ and AGND (decreases FSR) or REFADJ and REFIO (increases FSR). If REFADJ is connected to AVCC, the internal reference can be overdriven with an external source connected to REFIO. If REFADJ is connected to AGND, the internal reference is used to determine the FSR of the data converter. Positive Analog Input Terminal Negative Analog Input Terminal Clock Divider Input. This LVCMOS-compatible input controls which speed the converter's digital outputs are updated with. CLKDIV has an internal pulldown resistor. CLKDIV = 0: ADC updates digital outputs at one-half the input clock rate. CLKDIV = 1: ADC updates digital outputs at input clock rate. True Clock Input. This input ideally requires an LVPECL-compatible input level to maintain the converter's excellent performance. Complementary Clock Input. This input ideally requires an LVPECL-compatible input level to maintain the converter's excellent performance. Digital Converter Ground. Ground connection for digital circuitry and output drivers. Digital Supply Voltage. Bypass with a 0.1F capacitor for best decoupling results. Complementary Output Bit 0 (LSB) True Output Bit 0 (LSB) Complementary Output Bit 1 True Output Bit 1 Complementary Output Bit 2 True Output Bit 2 Complementary Output Bit 3 True Output Bit 3
4
REFADJ
8 9
INP INN
17
CLKDIV
22 23 26, 45, 61 27, 28, 41, 44, 60 29 30 31 32 33 34 35 36
CLKP CLKN OGND OVCC D0N D0P D1N D1P D2N D2P D3N D3P
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9
1.8V, 12-Bit, 170Msps ADC for Broadband Applications MAX1213
Pin Description (continued)
PIN 37 38 39 40 42 43 46 47 48 49 50 51 52 53 54 55 56 57 58 59 NAME D4N D4P D5N D5P DCLKN DCLKP D6N D6P D7N D7P D8N D8P D9N D9P D10N D10P D11N D11P ORN ORP Complementary Output Bit 4 True Output Bit 4 Complementary Output Bit 5 True Output Bit 5 Complementary Clock Output. This output provides an LVDS-compatible output level and can be used to synchronize external devices to the converter clock. True Clock Output. This output provides an LVDS-compatible output level and can be used to synchronize external devices to the converter clock. Complementary Output Bit 6 True Output Bit 6 Complementary Output Bit 7 True Output Bit 7 Complementary Output Bit 8 True Output Bit 8 Complementary Output Bit 9 True Output Bit 9 Complementary Output Bit 10 True Output Bit 10 Complementary Output Bit 11 (MSB) True Output Bit 11 (MSB) Complementary Output for Out-of-Range Control Bit. If an out-of-range condition is detected, bit ORN flags this condition by transitioning low. True Output for Out-of-Range Control Bit. If an out-of-range condition is detected, bit ORP flags this condition by transitioning high. Two's Complement or Binary Output Format Selection. This LVCMOS-compatible input controls the digital output format of the MAX1213. T/B has an internal pulldown resistor. T/B = 0: Two's complement output format. T/B = 1: Binary output format. Exposed Paddle. The exposed paddle is located on the backside of the chip and must be connected to analog group for optimum performance. FUNCTION
68
T/B
--
EP
10
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1.8V, 12-Bit, 170Msps ADC for Broadband Applications MAX1213
CLKDIV DCLKP DCLKN
CLKP CLKN INP INN 2.2k
CLOCKDIVIDER CONTROL INPUT BUFFER
CLOCK MANAGEMENT 12-BIT PIPELINE QUANTIZER CORE
T/H
LVDS DATA PORT 12
D0P/N-D11P/N
2.2k
COMMON-MODE BUFFER
ORP ORN REFERENCE
MAX1213
REFIO
REFADJ
Figure 1. Simplified MAX1213 Block Diagram
Detailed Description-- Theory of Operation
The MAX1213 uses a fully differential pipelined architecture that allows for high-speed conversion, optimized accuracy, and linearity while minimizing power consumption and die size. Both positive (INP) and negative/complementary analog input terminals (INN) are centered around a common-mode voltage of 1.365V, and accept a differential analog input voltage swing of 0.371V each, resulting in a typical differential full-scale signal swing of 1.485VP-P. Inputs INP and INN are buffered prior to entering each T/H stage and are sampled when the differential sampling clock signal transitions high. Each pipeline converter stage converts its input voltage to a digital output code. At every stage, except the last, the error between the input voltage and the digital output code is multiplied and passed along to the next pipeline stage. Digital error correction compensates for ADC comparator offsets in each pipeline stage and ensures no missing codes. The result is a 12-bit parallel digital output word in user-selectable two's complement or offset binary output formats with LVDS-compatible output levels. See Figure 1 for a more detailed view of the MAX1213 architecture.
INP 2.2k 2.2k
AVCC
INN
TO COMMON MODE
TO COMMON MODE AGND
+371mV
1.485VP-P DIFFERENTIAL FSR
+371mV
-371mV
-371mV
INN
COMMON-MODE VOLTAGE (1.365V)
Analog Inputs (INP, INN)
INP and INN are the fully differential inputs of the MAX1213. Differential inputs usually feature good rejection of even-order harmonics, which allows for enhanced AC performance as the signals are progressing through the analog stages. The MAX1213 analog inputs are self-biased at a common-mode voltage of 1.365V and allow a differential input voltage swing of 1.485V P-P (Figure 2). Both inputs are self-biased
Figure 2. Simplified Analog Input Architecture and Allowable Input Voltage Range
through 2k resistors, resulting in a typical differential input resistance of 4k. It is recommended to drive the analog inputs of the MAX1213 in AC-coupled configuration to achieve best dynamic performance. See the Transformer-Coupled, Differential Analog Input Drive section for a detailed discussion of this configuration.
______________________________________________________________________________________
742mVP-P
742mVP-P
INP
COMMON-MODE VOLTAGE (1.365V)
11
1.8V, 12-Bit, 170Msps ADC for Broadband Applications MAX1213
On-Chip Reference Circuit
The MAX1213 features an internal 1.24V bandgap reference circuit (Figure 3), which in combination with an internal reference-scaling amplifier determines the FSR of the MAX1213. Bypass REFIO with a 0.1F capacitor to AGND. To compensate for gain errors or increase the ADC's FSR, the voltage of this bandgap reference can be indirectly adjusted by adding an external resistor (e.g., 100k trim potentiometer) between REFADJ and AGND or REFADJ and REFIO. See the Applications Information section for a detailed description of this process. To disable the internal reference, connect REFADJ to AVCC. In this configuration, an external, stable reference must be applied to REFIO to set the converter's full scale. To enable the internal reference, connect REFADJ to AGND. The MAX1213 also features an internal clock-management circuit (duty-cycle equalizer) that ensures that the clock signal applied to inputs CLKP and CLKN is processed to provide a 50% duty-cycle clock signal that desensitizes the performance of the converter to variations in the duty cycle of the input clock source. Note that the clock duty-cycle equalizer cannot be turned off externally and requires a minimum clock frequency of >20MHz to work appropriately and according to data sheet specifications.
Clock Outputs (DCLKP, DCLKN)
The MAX1213 features a differential clock output, which can be used to latch the digital output data with an external latch or receiver. Additionally, the clock output can be used to synchronize external devices (e.g., FPGAs) to the ADC. DCLKP and DCLKN are differential outputs with LVDS-compatible voltage levels. There is a 4.815ns delay time between the rising (falling) edge of CLKP (CLKN) and the rising edge of DCLKP (DCLKN). See Figure 4 for timing details.
Clock Inputs (CLKP, CLKN)
Designed for a differential LVDS clock input drive, it is recommended to drive the clock inputs of the MAX1213 with an LVDS-compatible clock to achieve the best dynamic performance. The clock signal source must be a high-quality, low-phase noise to avoid any degradation in the noise performance of the ADC. The clock inputs (CLKP, CLKN) are internally biased to 1.15V, accept a typical differential signal swing of 0.5VP-P, and are usually driven in AC-coupled configuration. See the Differential, AC-Coupled PECL-Compatible Clock Input section for more circuit details on how to drive CLKP and CLKN appropriately. Although not recommended, the clock inputs also accept a single-ended input signal.
Divide-by-2 Clock Control (CLKDIV)
The MAX1213 offers a clock control line (CLKDIV), which supports the reduction of clock jitter in a system. Connect CLKDIV to OGND to enable the ADC's internal divide-by-2 clock divider. Data is now updated at onehalf the ADC's input clock rate. CLKDIV has an internal pulldown resistor and can be left open for applications that require this divide-by-2 mode. Connecting CLKDIV to OVCC disables the divide-by-2 mode.
REFT ADC FULL SCALE = REFT-REFB REFERENCE BUFFER REFB G
REFERENCE SCALING AMPLIFIER
1V
REFIO 0.1F REFADJ
CONTROL LINE TO DISABLE REFERENCE BUFFER
100*
MAX1213
AVCC REFT: TOP OF REFERENCE LADDER. REFB: BOTTOM OF REFERENCE LADDER. AVCC/2
*REFADJ MAY BE SHORTED TO AGND DIRECTLY
Figure 3. Simplified Reference Architecture 12 ______________________________________________________________________________________
1.8V, 12-Bit, 170Msps ADC for Broadband Applications
System Timing Requirements
Figure 4 depicts the relationship between the clock input and output, analog input, sampling event, and data output. The MAX1213 samples on the rising (falling) edge of CLKP (CLKN). Output data is valid on the next rising (falling) edge of the DCLKP (DCLKN) clock, but has an internal latency of 11 clock cycles. mat. All LVDS outputs provide a typical voltage swing of 0.371V around a common-mode voltage of roughly 1.2V, and must be terminated at the far end of each transmission line pair (true and complementary) with 100. The LVDS outputs are powered from a separate power supply, which can be operated between 1.7V and 1.9V. The MAX1213 offers an additional differential output pair (ORP, ORN) to flag out-of-range conditions, where out-of-range is above positive or below negative full scale. An out-of-range condition is identified with ORP (ORN) transitioning high (low). Note: Although a differential LVDS output architecture reduces single-ended transients to the supply and ground planes, capacitive loading on the digital outputs should still be kept as low as possible. Using LVDS buffers on the digital outputs of the ADC when driving larger loads may improve overall performance and reduce system-timing constraints.
MAX1213
Digital Outputs (D0P/N-D11P/N, DCLKP/N, ORP/N) and Control Input T/B
Digital outputs D0P/N-D11P/N, DCLKP/N, and ORP/N are LVDS compatible, and data on D0P/N-D11P/N is presented in either binary or two's-complement format (Table 1). The T/B control line is an LVCMOS-compatible input, which allows the user to select the desired output format. Pulling T/B low outputs data in two's complement and pulling it high presents data in offset binary format on the 12-bit parallel bus. T/B has an internal pulldown resistor and may be left unconnected in applications using only two's complement output for-
SAMPLING EVENT
SAMPLING EVENT
SAMPLING EVENT
SAMPLING EVENT
INN
INP tAD CLKN N CLKP tCPDL tLATENCY DCLKP N-8 DCLKN tPDL tCPDL - tPDL N-7 N N+1 N+1 N+8 N+9 tCH tCL
D0P/N- D11P/N ORP/N
N-8
N-7
N-1
N
N+1
tPDL - tPDL~ 0.4 x tSAMPLE WITH tSAMPLE = 1/fSAMPLE NOTE: THE ADC SAMPLES ON THE RISING EDGE OF CLKP. THE RISING EDGE OF DCLKP CAN BE USED TO EXTERNALLY LATCH THE OUTPUT DATA.
Figure 4. System and Output Timing Diagram ______________________________________________________________________________________ 13
1.8V, 12-Bit, 170Msps ADC for Broadband Applications MAX1213
Table 1. MAX1213 Digital Output Coding
INP ANALOG INPUT VOLTAGE LEVEL > VCM + 0.371V VCM + 0.371V VCM VCM - 0.371V < VCM + 0.371V INN ANALOG INPUT VOLTAGE LEVEL < VCM - 0.371V VCM - 0.371V VCM VCM + 0.371V > VCM - 0.371V OUT-OF-RANGE ORP (ORN) 1 (0) 0 (1) 0 (1) 0 (1) 1 (0) BINARY DIGITAL OUTPUT CODE (D11P/N-D0P/N) 1111 1111 1111 (exceeds +FS, OR set) 1111 1111 1111 (+FS) 1000 0000 0000 or 0111 1111 1111 (FS/2) 0000 0000 0000 (-FS) 00 0000 0000 (exceeds -FS, OR set) TWO'S COMPLEMENT DIGITAL OUTPUT CODE (D11P/N-D0P/N) 0111 1111 1111 (exceeds +FS, OR set) 0111 1111 1111 (+FS) 0000 0000 0000 or 1111 1111 1111 (FS/2) 1000 0000 0000 (-FS) 10 0000 0000 (exceeds -FS, OR set)
OVCC
REFT ADC FULL SCALE = REFT-REFB REFERENCE BUFFER 1V
VOP VON
G REFB
REFERENCE SCALING AMPLIFIER
REFIO 0.1F 13k TO 1M
2.2k
2.2k
REFADJ CONTROL LINE TO DISABLE REFERENCE BUFFER
13k TO 1M
OGND
MAX1213
AVCC
AVCC/2
Figure 5. Simplified LVDS Output Architecture
REFT: TOP OF REFERENCE LADDER. REFB: BOTTOM OF REFERENCE LADDER.
Applications Information
FSR Adjustments Using the Internal Bandgap Reference
The MAX1213 supports a full-scale adjustment range of 10% (5%). To decrease the full-scale signal range, an external resistor value ranging from 13k to 1M may be added between REFADJ and AGND. A similar approach can be taken to increase the ADC's full-scale signal range. Adding a variable resistor, potentiometer, or predetermined resistor value between REFADJ and REFIO increases the FSR of the data converter. Figure 6a shows the two possible configurations and their impact on the overall full-scale range adjustment of the MAX1213. Do not use resistor values of less than 13k to avoid instability of the internal gain regulation loop for the bandgap reference. See Figure 6b for the results of the adjustment range for a selection of resistors used to trim the full-scale range of the MAX1213.
14
Figure 6a: Circuit Suggestions to Adjust the ADC's Full-Scale Range
FS VOLTAGE vs. FS ADJUST RESISTOR
1.33 1.31 1.29 VFS (V) 1.27 1.25 1.23 1.21 1.19 1.17 1.15 0 125 250 375 500 625 750 875 1000 FS ADJUST RESISTOR () RESISTOR VALUE APPLIED BETWEEN REFADJ AND AGND DECREASES VFS RESISTOR VALUE APPLIED BETWEEN REFADJ AND REFIO INCREASES VFS
MAX1213 fig06b
1.35
Figure 6b: FS Adjustment Range vs. FS Adjustment Resistor
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1.8V, 12-Bit, 170Msps ADC for Broadband Applications
Differential, AC-Coupled, LVPECL-Compatible Clock Input
The MAX1213 dynamic performance depends on the use of a very clean clock source. The phase noise floor of the clock source has a negative impact on the SNR performance. Spurious signals on the clock signal source also affect the ADC's dynamic range. The preferred method of clocking the MAX1213 is differentially with LVDS- or LVPECL-compatible input levels. The fast data transition rates of these logic families minimize the clock-input circuitry's transition uncertainty, thereby improving the SNR performance. To accomplish this, a 50 reverse-terminated clock signal source with low phase noise is AC-coupled into a fast differential receiver such as the MC100LVEL16 (Figure 7). The receiver produces the necessary LVPECL output levels to drive the clock inputs of the data converter. commended to drive the ADC inputs in single-ended configuration. In differential input mode, even-order harmonics are usually lower since INP and INN are balanced, and each of the ADC inputs only requires half the signal swing compared to a single-ended configuration. Wideband RF transformers provide an excellent solution to convert a single-ended signal to a fully differential signal, required by the MAX1213 to reach its optimum dynamic performance. A secondary-side termination of a 1:1 transformer (e.g., Mini-Circuit's ADT1-1WT) into two separate 24.9 1% resistors (use tight resistor tolerances to minimize effects of imbalance; 0.5% would be an ideal choice) placed between top/bottom and center tap of the transformer is recommended to maximize the ADC's dynamic range. This configuration optimizes THD and SFDR performance of the ADC by reducing the effects of transformer parasitics. However, the source impedance combined with the shunt capacitance provided by a PC board and the ADC's parasitic capacitance limit the ADC's full-power input bandwidth to approximately 600MHz.
MAX1213
Transformer-Coupled, Differential Analog Input Drive
In general, the MAX1213 provides the best SFDR and THD with fully differential input signals and it is not re-
VCLK 0.1F SINGLE-ENDED INPUT TERMINAL 8 0.1F 2 7 150 50 MC100LVEL16 0.1F 3 510 510 4 5 6 150 AVCC OVCC 0.1F
0.01F VGND
INP
CLKN CLKP D0P/N-D11P/N
MAX1213
INN 12
AGND OGND
Figure 7. Differential, AC-Coupled, PECL-Compatible Clock Input Configuration
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15
1.8V, 12-Bit, 170Msps ADC for Broadband Applications MAX1213
To further enhance THD and SFDR performance at high-input frequencies (>100MHz), a second transformer (Figure 8) should be placed in series with the single-ended-to-differential conversion transformer. This transformer reduces the increase of even-order harmonics at high frequencies.
Grounding, Bypassing, and Board Layout Considerations
The MAX1213 requires board layout design techniques suitable for high-speed data converters. This ADC provides separate analog and digital power supplies. The analog and digital supply voltage pins accept input voltage ranges of 1.7V to 1.9V. Although both supply types can be combined and supplied from one source, it is recommended to use separate sources to cut down on performance degradation caused by digital switching currents, which can couple into the analog supply network. Isolate analog and digital supplies (AVCC and OVCC) where they enter the PC board with separate networks of ferrite beads and capacitors to their corresponding grounds (AGND, OGND).
Single-Ended, AC-Coupled Analog Inputs
Although not recommended, the MAX1213 can be used in single-ended mode (Figure 9). Analog signals can be AC-coupled to the positive input INP through a 0.1F capacitor and terminated with a 49.9 resistor to AGND. The negative input should be reverse terminated with 24.9 resistors and AC-grounded with a 0.1F capacitor.
AVCC 10 0.1F ADT1-1WT ADT1-1WT 25
OVCC
SINGLE-ENDED INPUT TERMINAL
INP D0P/N-D11P/N
MAX1213
25 10 INN 12
0.1F
AGND
OGND
Figure 8. Analog Input Configuration with Back-to-Back Transformers and Secondary-Side Termination
AVCC SINGLE-ENDED INPUT TERMINAL
OVCC
0.1F
INP D0P/N-D11P/N
50 0.1F
MAX1213
INN 12
25
AGND
OGND
Figure 9. Single-Ended AC-Coupled Analog Input Configuration
16
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1.8V, 12-Bit, 170Msps ADC for Broadband Applications
To achieve optimum performance, provide each supply with a separate network of a 47F tantalum capacitor and parallel combinations of 10F and 1F ceramic capacitors. Additionally, the ADC requires each supply pin to be bypassed with separate 0.1F ceramic capacitors (Figure 10). Locate these capacitors directly at the ADC supply pins or as close as possible to the MAX1213. Choose surface-mount capacitors, whose preferred location should be on the same side as the converter to save space and minimize the inductance. If close placement on the same side is not possible, these bypassing capacitors may be routed through vias to the bottom side of the PC board. Multilayer boards with separated ground and power planes produce the highest level of signal integrity. Consider the use of a split ground plane arranged to match the physical location of analog and digital ground on the ADC's package. The two ground planes should be joined at a single point such that the noisy digital ground currents do not interfere with the analog ground plane. The dynamic currents that may need to travel long distances before they are recombined at a common-source ground, resulting in large and undesirable ground loops, are a major concern with this approach. Ground loops can degrade the input noise by coupling back to the analog front end of the converter, resulting in increased spurious activity, leading to decreased noise performance. Alternatively, all ground pins could share the same ground plane, if the ground plane is sufficiently isolated from any noisy, digital systems ground. To minimize the coupling of the digital output signals from the analog input, segregate the digital output bus carefully from the
BYPASSING-ADC LEVEL AVCC OVCC
analog input circuitry. To further minimize the effects of digital noise coupling, ground return vias can be positioned throughout the layout to divert digital switching currents away from the sensitive analog sections of the ADC. This approach does not require split ground planes, but can be accomplished by placing substantial ground connections between the analog front end and the digital outputs. The MAX1213 is packaged in a 68-pin QFN-EP package (package code: G6800-4), providing greater design flexibility, increased thermal dissipation, and optimized AC performance of the ADC. The exposed paddle (EP) must be soldered down to AGND. In this package, the data converter die is attached to an EP lead frame with the back of this frame exposed at the package bottom surface, facing the PC board side of the package. This allows a solid attachment of the package to the board with standard infrared (IR) flow soldering techniques. Thermal efficiency is one of the factors for selecting a package with an exposed pad for the MAX1213. The exposed pad improves thermal and ensures a solid ground connection between the DAC and the PC board's analog ground layer. Considerable care must be taken when routing the digital output traces for a high-speed, high-resolution data converter. It is essential to keep trace lengths at a minimum and place minimal capacitive loading--less than 5pF--on any digital trace to prevent coupling to sensitive analog sections of the ADC. It is recommended running the LVDS output traces as differential lines with 100 characteristic impedance from the ADC to the LVDS load device.
BYPASSING-BOARD LEVEL AVCC
MAX1213
0.1F
0.1F 1F 10F 47F
ANALOG POWERSUPPLY SOURCE
AGND
OGND D0P/N-D11P/N
OVCC
MAX1213
12 1F NOTE: EACH POWER-SUPPLY PIN (ANALOG AND DIGITAL) SHOULD BE DECOUPLED WITH AN INDIVIDUAL 0.1F CAPACITOR AS CLOSE AS POSSIBLE TO THE ADC. 10F 47F DIGITAL/OUTPUT DRIVER POWERSUPPLY SOURCE
AGND
OGND
Figure 10. Grounding, Bypassing, and Decoupling Recommendations for MAX1213 ______________________________________________________________________________________ 17
1.8V, 12-Bit, 170Msps ADC for Broadband Applications MAX1213
Static Parameter Definitions
Integral Nonlinearity (INL)
Integral nonlinearity is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best straight-line fit or a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. However, the static linearity parameters for the MAX1213 are measured using the histogram method with an input frequency of 10MHz. tion error only and results directly from the ADC's resolution (N bits): SNR[max] = 6.02 x N + 1.76 In reality, other noise sources such as thermal noise, clock jitter, signal phase noise, and transfer function nonlinearities are also contributing to the SNR calculation and should be considered when determining the signal-to-noise ratio in ADC.
Signal-to-Noise Plus Distortion (SINAD)
SINAD is computed by taking the ratio of the RMS signal to all spectral components excluding the fundamental and the DC offset. In the case of the MAX1213, SINAD is computed from a curve fit.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between an actual step width and the ideal value of 1LSB. A DNL error specification of less than 1LSB guarantees no missing codes and a monotonic transfer function. The MAX1213's DNL specification is measured with the histogram method based on a 10MHz input tone.
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio of RMS amplitude of the carrier frequency (maximum signal component) to the RMS value of the next-largest noise or harmonic distortion component. SFDR is usually measured in dBc with respect to the carrier frequency amplitude or in dBFS with respect to the ADC's full-scale range.
Dynamic Parameter Definitions
Aperture Jitter
Figure 11 depicts the aperture jitter (tAJ), which is the sample-to-sample variation in the aperture delay.
Intermodulation Distortion (IMD)
IMD is the ratio of the RMS sum of the intermodulation products to the RMS sum of the two fundamental input tones. This is expressed as: VIM12 + VIM22 + ...... + VIM32 + VIMn2 IMD = 20 x log V12 + V22
Aperture Delay
Aperture delay (tAD) is the time defined between the rising edge of the sampling clock and the instant when an actual sample is taken (Figure 11).
CLKP CLKN
ANALOG INPUT tAD tAJ SAMPLED DATA (T/H)
The fundamental input tone amplitudes (V1 and V2) are at -7dBFS. The intermodulation products are the amplitudes of the output spectrum at the following frequencies: * Second-order intermodulation products: fIN1 + fIN2, fIN2 - fIN1 * Third-order intermodulation products: 2 x fIN1 - fIN2, 2 x fIN2 - fIN1, 2 x fIN1 + fIN2, 2 x fIN2 + fIN1 * Fourth-order intermodulation products: 3 x fIN1 - fIN2, 3 x fIN2 - fIN1, 3 x fIN1 + fIN2, 3 x fIN2 + fIN1 * Fifth-order intermodulation products: 3 x fIN1 - 2 x fIN2, 3 x fIN2-2 x fIN1, 3 x fIN1+2 x fIN2, 3 x fIN2 + 2 x fIN1
T/H
TRACK
HOLD
TRACK
Figure11. Aperture Jitter/Delay Specifications
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantiza-
Full-Power Bandwidth
A large -1dBFS analog input signal is applied to an ADC and the input frequency is swept up to the point where the amplitude of the digitized conversion result has decreased by 3dB. The -3dB-point is defined as full-power input bandwidth frequency of the ADC.
18
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1.8V, 12-Bit, 170Msps ADC for Broadband Applications
Noise Power Ratio (NPR)
NPR is commonly used to characterize the return path of cable systems where the signals are typically individual quadrature amplitude-modulated (QAM) carriers with a frequency spectrum similar to noise. Numerous such carriers are operated in a continuous spectrum, generating a noise-like signal, which covers a relatively broad bandwidth. To test the MAX1213 for NPR, a "noise-like" signal is passed through a high-order bandpass filter to produce an approximately square spectral pedestal of noise with about the same bandwidth as the signals being simulated. Following the bandpass filter, the signal is passed through a narrow band-reject filter to produce a deep notch at the center of the noise pedestal. Finally, this signal is applied to the MAX1213 and its digitized results analyzed. The RMS noise power of the signal inside the notch is compared with the RMS noise level outside the notch using an FFT. Note that the NPR test requires sufficiently long data records to guarantee a suitable number of samples inside the notch. NPR for the MAX1213 was determined for 35MHz and 50MHz noise bandwidth signals, simulating a typical cable signal environment (see the Typical Operating Characteristics for test details and results).
Pin-Compatible Lower Speed/Resolution Versions
Applications that require lower resolution and/or higher speed can refer to other family members of the MAX1213. Adjusting an application to a lower resolution has been simplified by maintaining an identical pinout for all members of this high-speed family. See Table 2 for a selection of different resolution and speed grades.
MAX1213
Table 2. Selection of Lower Resolution/ Higher Speed Versions of the MAX1213
PART MAX1121 MAX1122 MAX1123 MAX1124 RESOLUTION (BITS) 8 10 10 10 SPEED GRADE (Msps) 250 170 210 250
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19
1.8V, 12-Bit, 170Msps ADC for Broadband Applications MAX1213
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) 68L QFN.EPS
PACKAGE OUTLINE, 68L QFN, 10x10x0.9 MM C 12 21-0122
20
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1.8V, 12-Bit, 170Msps ADC for Broadband Applications
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
MAX1213
PACKAGE OUTLINE, 68L QFN, 10x10x0.9 MM C 12 21-0122
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 21 (c) 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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